Mémoire flash, 256Mbit, 32M x 8 bits, SPI, BGA, 24 broches

Serial Peripheral Interface (SPI) with Multi-I/O
Clock polarity and phase modes 0 and 3
Double Data Rate (DDR) option
Quad peripheral Interface (QPI) option
Extended Addressing: 24- or 32-bit address options
Serial Command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
Multi I/O Command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families
Read
Commands: Normal, Fast, Dual I/O, Quad I/O, DualO,QuadO, DDR Quad I/O.
Modes: Burst Wrap, Continuous (XIP), QPI
Serial Flash Discoverable Parameters (SFDP) for configuration information.
Program Architecture
256 Bytes Page Programming buffer
3.0 V FL-L Flash Memory
Program suspend and resume
Erase Architecture
Uniform 4 KB Sector Erase
Uniform 32 KB Half Block Erase
Uniform 64 KB Block Erase
Chip erase
Erase suspend and resume
100,000 Program/Erase Cycles, minimum
20 ans de conservation des données
Caractéristiques de sécurité
Status and Configuration Register Protection
Four Security Regions of 256 bytes each outside the main
Flash array
Legacy Block Protection: Block range
Individual and Region Protection
Individual Block Lock: Volatile individual Sector/Block
Pointer Region: Non-Volatile Sector/Block range
Power Supply Lock-down, Password, or Permanent protection of Security Regions 2 and 3 and Pointer Region
Technologie
65 nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
2,7 V, 3,6 V
Packages (all Pb-free)
8-pin SOIC 208 mil (SOC008) — S25FL128L only
WSON 5 x 6 mm (WND008) — S25FL128L only
WSON 6 x 8 mm (WNG008) — S25FL256L only
16-pin SOIC 300 mil (SO3016)
BGA-24 6 x 8 mm
5 x 5 ball (FAB024) footprint
4 x 6 ball (FAC024) footprint